New lower-cost memory solution for 5G cellular modems
To support high-speed operation and high data-transfer rates, a wireless cellular modem requires an advanced baseband processor architecture that includes high-speed main memory backed by capacity sufficient to store the large code base of the modem’s protocol software.
The 5G modems on the market today are able to implement this architecture with a hardware design that includes a combination of 1.8V NAND Flash and 1.8V Low-Power DDR4x (LPDDR4x) devices housed in a single multi-chip package (MCP).
While LPDDR5 is the latest version of low-power synchronous DRAM (SDRAM) main memory technology. The next most recent generation of the technology – LPDDR4x – is, by contrast, widely available. In 5G modems, it provides the combination of low-power operation and high data-transfer rates required by the cellular mobile processor chipsets supplied by manufacturers such as Qualcomm, Samsung, Huawei and Mediatek.
The new 1.8V 2Gb+2Gb NAND Flash and LPDDR4x memory product from Winbond is a compact 8.0 x 9.5 x 0.8mm multi-chip package (MCP). The new W71NW20KK1KW, which combines robust Single Level Cell (SLC) NAND Flash and high-speed, low-power LPDDR4x memory, provides sufficient memory capacity for 5G cellular modems that are intended for use as Customer Premises Equipment (CPE) in homes and offices.
While mobile 5G modems typically require larger memory densities, static 5G CPE modems can operate perfectly with memory capacities of 2Gb NAND/2Gb DRAM. By offering this memory combination in a compact single package, Winbond’s W71NW20KK1KW enables 5G modem manufacturers to meet the system requirements of CPE units at the lowest possible materials and production cost.
It is expected that the introduction of a new generation of cost-optimized 5G CPE units incorporating the W71NW20KK1KW will help to accelerate consumer adoption of 5G as an alternative to fixed-line copper or optical xDSL links in the last mile of high-speed broadband networks.
The W71NW20KK1KW is a 149-ball Ball Grid Array (BGA) MCP consisting of a 2Gb SLC NAND Flash die and a 2Gb LPDDR4x DRAM die. The robust SLC NAND Flash offers excellent endurance specifications and high data integrity. The SLC NAND only requires 4-bit ECC to achieve high data integrity, but the device’s 2KB+128B page size provides enough space for the use of 8-bit ECC.
The W71NW20KK1KW has an 8-bit bus, and is organized in blocks of 64 pages. The NAND die’s performance specifications include a maximum page Read time of 25µs and a typical page program time of 250µs.
The LPDDR4x DRAM die, which operates at a high frequency of 1866MHz, provides an LVSTL_11 interface and features eight internal banks for concurrent operation. It offers a data rate of up to 4267MT/s, supporting the fast data-transfer rates to be offered by 5G cellular networks.
- Density : 2Gbit (Single chip solution)
- Vcc : 1.7V to 1.95V
- Bus width : x8
- Operating temperature Industrial: -40°C to 85°C
- Page size:2,176 bytes (2048 + 128 bytes)
- Block size:64 pages(128K + 8K bytes)
- Lowest power consumption
- Read:13mA (typ.)
- Program/Erase: 10mA (typ.)
- CMOS standby: 10uA (typ.)
- Data width: x16
- Clock rate: up to 2133 MHz2
- Interface: LVSTL_11